Farò progetti rtl usando vhdl, verilog e systemverilog

Proactive in trying to correct any correction I asked to. Had some differences in understanding of certain subjects but overall decent.

great experice

good tutor

my project was designing a CPU with an n bit instruction size, i had only two days before the deadline,, and i received a file that i was not satisfied with 4 hours before submission so i didnt use it and used my own files instead…..could be my fault for having a short deadline but i excepted more 🙅🏻‍♀️.

Professional, paid attention to all details. In the end a high quality product was delivered.