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esha_sci

Esha

@esha_sci

FPGA, Verilog, MATLAB and Python Engineer

Corea del Sud
Inglese, Urdu
Alcune informazioni sono riportate in lingua inglese.
Chi sono
I am an engineering researcher and developer specializing in FPGA design, Verilog/SystemVerilog, MATLAB, Python, and engineering simulations. I work with RTL design, testbenches, functional simulation, debugging, FPGA synthesis, and Xilinx Vivado. I also develop MATLAB and Python solutions for signal processing, wireless communications, data analysis, machine learning, and scientific visualization. I provide technical research support including proofreading, formatting, figures, tables, and result visualization, with a focus on clear code and professional work.... Continua a leggere

Competenze

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esha_sci
Esha
offline • 

Consulta i miei servizi

Sistemi integrati e IoT
I will design, simulate and debug verilog fpga rtl modules