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pmaddhyeshia

Preeti

@pmaddhyeshia

VLSI Engineer, Verilog, SV, UVM

India
Inglese, Hindi
Alcune informazioni sono riportate in lingua inglese.
Chi sono
I am a VLSI engineer with MTech in VLSI Design and CDAC certification. I have hands-on experience in Verilog, SystemVerilog, and basic verification. I help students and professionals with: VLSI assignments and projects Verilog/SystemVerilog coding Testbench development UVM basics and debugging Simulation and error fixing I focus on delivering accurate and high-quality work within deadlines. Feel free to contact me before placing an order.... Continua a leggere

Competenze

p
pmaddhyeshia
Preeti
offline • 
Tempo di risposta medio: 1 ora

Consulta i miei servizi

Sistemi integrati e IoT
I will in verilog, digital design, system verilog and uvm tasks
A partire da10 USD / progettoMaggiori dettagli

Esperienza lavorativa

Verification Engineer

Alpha - Numero a Quest Global

Nov 2024 - Apr 2025 • 5 mos

I worked as a Trainee Verification Engineer where I gained hands-on experience in Verilog and SystemVerilog. I have successfully worked on design and verification of: RAM (Random Access Memory) Synchronous FIFO My work included writing RTL code, developing basic testbenches, performing simulations, and debugging design issues. I also gained understanding of functional verification concepts and waveform analysis. I am confident in handling VLSI design and verification tasks with accuracy. I have successfully completed design and verification projects including RAM and Synchronous FIFO using Verilog/SystemVerilog. These projects helped me build strong skills in RTL design, debugging, and simulation. I have also completed MTech in VLSI Design and CDAC certification, strengthening my technical foundation.