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ChipCraftPro
@soniyakiran
Physical Design Engineer
Pakistan
Chi sono
Senior Physical Design Engineer with 3+ years in VLSI/ASIC design flows. I specialize in floorplanning, placement & routing, timing closure, and EDA automation using Cadence Innovus and Synopsys ICC2.
I combine deep hardware expertise with Python/TCL scripting and machine learning to deliver automation tools that save design teams significant hours. I also write clear, professional technical documentation for ASIC and FPGA projects.
Available for short, focused side projects — fast turnaround guaranteed.
ChipCraftPro
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I will write tcl python eda automation scripts for cadence and synopsys
