Sfoglia categorie
Esplora
Fiverr Pro
Italiano
$
USD
Sujit
@sujit100205
RTL Design Engineer Verilog FPGA RISC V
India
Inglese, Hindi
Chi sono
I am an RTL Design Engineer with experience in Verilog/SystemVerilog, FPGA development, and digital system design. I have worked on projects including RISC-V processor design, custom instruction sets, and FPGA implementation on platforms like Basys 3.
I offer RTL design, testbench creation, simulation, FPGA debugging, and optimization. I focus on writing clean, synthesizable code with reliable results. I can assist with both academic and professional projects. Feel free to reach out to discuss your requirements.
Competenze
Sujit
offline •
Tempo di risposta medio: 1 ora
Consulta i miei servizi
Sistemi integrati e IoT
I will design rtl in verilog for fpga
